1. Field of the Invention
The present invention relates to dielectric isolation structures for semiconductor devices, and more particularly to dielectric isolation structures fabricated using ultra high energy buried implants.
2. Description of Related Art
Dielectric substrate isolation is particularly useful in high voltage power integrated circuits and radiation hardened devices. Devices fabricated with the alternative junction isolation technology suffer poor breakdown performance by comparison.
One class of dielectric isolated substrate techniques generally involves the formation of v-shaped isolation moats in one surface of a single crystal silicon wafer and the subsequent deposition thereon of a relatively thick layer or layers of polysilicon. The single crystals is then precision lapped and polished from the other surface, until dielectric isolated islands of single crystal material emerge. An early version of this technique is described in an article by Suzuki et al., "Deformation in Dielectric-Isolated Substrates and Its Control by a Multilayer Polysilicon Support Structure," J. Electrochem. Soc.: Solid-State Science and Technology, Vol. 127, No. 7, July 1980, pp.1537-1542. Note that this technique requires precision lapping and polishing, and the deposition of relatively thick polysilicon layers.
A technique that avoids the need for precision lapping and polishing is disclosed in U.S. Pat. No. 4,810,667, issued Mar. 7, 1989 to Zorinsky et al. The structure involves the deposition of multiple polysilicon layers, the first being a very heavily doped and porous N+ layer followed by other less heavily doped layers. Trenches are formed down to the N+ layer, and the N+ layer then is oxidized. Together, the oxide filled trenches and the oxidized N+ layer isolate the less heavily doped polysilicon layers, which form elements of subsequently fabricated devices. Unfortunately, this technique requires multiple depositions of doped polysilicon.